475 lines
13 KiB
C++
475 lines
13 KiB
C++
/*
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* Copyright 2018 Paul Stoffregen
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* Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of either the GNU General Public License version 2
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* or the GNU Lesser General Public License version 2.1, both as
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* published by the Free Software Foundation.
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*/
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#include <Arduino.h>
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#include "Ethernet.h"
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#include "w5100.h"
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/***************************************************/
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/** Default SS pin setting **/
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/***************************************************/
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// If variant.h or other headers specifically define the
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// default SS pin for ethernet, use it.
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#if defined(PIN_SPI_SS_ETHERNET_LIB)
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#define SS_PIN_DEFAULT PIN_SPI_SS_ETHERNET_LIB
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// MKR boards default to pin 5 for MKR ETH
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// Pins 8-10 are MOSI/SCK/MISO on MRK, so don't use pin 10
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#elif defined(USE_ARDUINO_MKR_PIN_LAYOUT) || defined(ARDUINO_SAMD_MKRZERO) || defined(ARDUINO_SAMD_MKR1000) || defined(ARDUINO_SAMD_MKRFox1200) || defined(ARDUINO_SAMD_MKRGSM1400) || defined(ARDUINO_SAMD_MKRWAN1300)
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#define SS_PIN_DEFAULT 5
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// For boards using AVR, assume shields with SS on pin 10
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// will be used. This allows for Arduino Mega (where
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// SS is pin 53) and Arduino Leonardo (where SS is pin 17)
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// to work by default with Arduino Ethernet Shield R2 & R3.
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#elif defined(__AVR__)
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#define SS_PIN_DEFAULT 10
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// If variant.h or other headers define these names
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// use them if none of the other cases match
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#elif defined(PIN_SPI_SS)
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#define SS_PIN_DEFAULT PIN_SPI_SS
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#elif defined(CORE_SS0_PIN)
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#define SS_PIN_DEFAULT CORE_SS0_PIN
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// As a final fallback, use pin 10
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#else
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#define SS_PIN_DEFAULT 10
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#endif
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// W5100 controller instance
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uint8_t W5100Class::chip = 0;
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uint8_t W5100Class::CH_BASE_MSB;
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uint8_t W5100Class::ss_pin = SS_PIN_DEFAULT;
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#ifdef ETHERNET_LARGE_BUFFERS
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uint16_t W5100Class::SSIZE = 2048;
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uint16_t W5100Class::SMASK = 0x07FF;
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#endif
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W5100Class W5100;
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// pointers and bitmasks for optimized SS pin
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#if defined(__AVR__)
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volatile uint8_t * W5100Class::ss_pin_reg;
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uint8_t W5100Class::ss_pin_mask;
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#elif defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__) || defined(__MK64FX512__)
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volatile uint8_t * W5100Class::ss_pin_reg;
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#elif defined(__MKL26Z64__)
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volatile uint8_t * W5100Class::ss_pin_reg;
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uint8_t W5100Class::ss_pin_mask;
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#elif defined(__SAM3X8E__) || defined(__SAM3A8C__) || defined(__SAM3A4C__)
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volatile uint32_t * W5100Class::ss_pin_reg;
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uint32_t W5100Class::ss_pin_mask;
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#elif defined(__PIC32MX__)
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volatile uint32_t * W5100Class::ss_pin_reg;
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uint32_t W5100Class::ss_pin_mask;
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#elif defined(ARDUINO_ARCH_ESP8266)
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volatile uint32_t * W5100Class::ss_pin_reg;
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uint32_t W5100Class::ss_pin_mask;
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#elif defined(__SAMD21G18A__)
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volatile uint32_t * W5100Class::ss_pin_reg;
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uint32_t W5100Class::ss_pin_mask;
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#endif
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uint8_t W5100Class::init(void)
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{
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static bool initialized = false;
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uint8_t i;
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if (initialized) return 1;
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// Many Ethernet shields have a CAT811 or similar reset chip
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// connected to W5100 or W5200 chips. The W5200 will not work at
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// all, and may even drive its MISO pin, until given an active low
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// reset pulse! The CAT811 has a 240 ms typical pulse length, and
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// a 400 ms worst case maximum pulse length. MAX811 has a worst
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// case maximum 560 ms pulse length. This delay is meant to wait
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// until the reset pulse is ended. If your hardware has a shorter
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// reset time, this can be edited or removed.
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delay(560);
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//Serial.println("w5100 init");
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SPI.begin();
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initSS();
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resetSS();
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SPI.beginTransaction(SPI_ETHERNET_SETTINGS);
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// Attempt W5200 detection first, because W5200 does not properly
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// reset its SPI state when CS goes high (inactive). Communication
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// from detecting the other chips can leave the W5200 in a state
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// where it won't recover, unless given a reset pulse.
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if (isW5200()) {
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CH_BASE_MSB = 0x40;
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#ifdef ETHERNET_LARGE_BUFFERS
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#if MAX_SOCK_NUM <= 1
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SSIZE = 16384;
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#elif MAX_SOCK_NUM <= 2
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SSIZE = 8192;
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#elif MAX_SOCK_NUM <= 4
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SSIZE = 4096;
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#else
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SSIZE = 2048;
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#endif
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SMASK = SSIZE - 1;
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#endif
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for (i=0; i<MAX_SOCK_NUM; i++) {
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writeSnRX_SIZE(i, SSIZE >> 10);
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writeSnTX_SIZE(i, SSIZE >> 10);
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}
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for (; i<8; i++) {
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writeSnRX_SIZE(i, 0);
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writeSnTX_SIZE(i, 0);
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}
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// Try W5500 next. Wiznet finally seems to have implemented
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// SPI well with this chip. It appears to be very resilient,
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// so try it after the fragile W5200
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} else if (isW5500()) {
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CH_BASE_MSB = 0x10;
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#ifdef ETHERNET_LARGE_BUFFERS
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#if MAX_SOCK_NUM <= 1
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SSIZE = 16384;
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#elif MAX_SOCK_NUM <= 2
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SSIZE = 8192;
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#elif MAX_SOCK_NUM <= 4
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SSIZE = 4096;
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#else
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SSIZE = 2048;
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#endif
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SMASK = SSIZE - 1;
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for (i=0; i<MAX_SOCK_NUM; i++) {
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writeSnRX_SIZE(i, SSIZE >> 10);
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writeSnTX_SIZE(i, SSIZE >> 10);
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}
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for (; i<8; i++) {
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writeSnRX_SIZE(i, 0);
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writeSnTX_SIZE(i, 0);
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}
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#endif
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// Try W5100 last. This simple chip uses fixed 4 byte frames
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// for every 8 bit access. Terribly inefficient, but so simple
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// it recovers from "hearing" unsuccessful W5100 or W5200
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// communication. W5100 is also the only chip without a VERSIONR
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// register for identification, so we check this last.
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} else if (isW5100()) {
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CH_BASE_MSB = 0x04;
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#ifdef ETHERNET_LARGE_BUFFERS
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#if MAX_SOCK_NUM <= 1
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SSIZE = 8192;
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writeTMSR(0x03);
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writeRMSR(0x03);
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#elif MAX_SOCK_NUM <= 2
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SSIZE = 4096;
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writeTMSR(0x0A);
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writeRMSR(0x0A);
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#else
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SSIZE = 2048;
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writeTMSR(0x55);
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writeRMSR(0x55);
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#endif
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SMASK = SSIZE - 1;
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#else
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writeTMSR(0x55);
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writeRMSR(0x55);
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#endif
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// No hardware seems to be present. Or it could be a W5200
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// that's heard other SPI communication if its chip select
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// pin wasn't high when a SD card or other SPI chip was used.
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} else {
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//Serial.println("no chip :-(");
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chip = 0;
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SPI.endTransaction();
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return 0; // no known chip is responding :-(
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}
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SPI.endTransaction();
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initialized = true;
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return 1; // successful init
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}
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// Soft reset the Wiznet chip, by writing to its MR register reset bit
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uint8_t W5100Class::softReset(void)
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{
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uint16_t count=0;
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//Serial.println("Wiznet soft reset");
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// write to reset bit
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writeMR(0x80);
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// then wait for soft reset to complete
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do {
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uint8_t mr = readMR();
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//Serial.print("mr=");
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//Serial.println(mr, HEX);
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if (mr == 0) return 1;
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delay(1);
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} while (++count < 20);
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return 0;
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}
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uint8_t W5100Class::isW5100(void)
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{
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chip = 51;
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//Serial.println("w5100.cpp: detect W5100 chip");
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if (!softReset()) return 0;
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writeMR(0x10);
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if (readMR() != 0x10) return 0;
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writeMR(0x12);
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if (readMR() != 0x12) return 0;
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writeMR(0x00);
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if (readMR() != 0x00) return 0;
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//Serial.println("chip is W5100");
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return 1;
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}
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uint8_t W5100Class::isW5200(void)
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{
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chip = 52;
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//Serial.println("w5100.cpp: detect W5200 chip");
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if (!softReset()) return 0;
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writeMR(0x08);
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if (readMR() != 0x08) return 0;
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writeMR(0x10);
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if (readMR() != 0x10) return 0;
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writeMR(0x00);
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if (readMR() != 0x00) return 0;
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int ver = readVERSIONR_W5200();
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//Serial.print("version=");
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//Serial.println(ver);
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if (ver != 3) return 0;
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//Serial.println("chip is W5200");
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return 1;
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}
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uint8_t W5100Class::isW5500(void)
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{
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chip = 55;
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//Serial.println("w5100.cpp: detect W5500 chip");
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if (!softReset()) return 0;
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writeMR(0x08);
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if (readMR() != 0x08) return 0;
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writeMR(0x10);
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if (readMR() != 0x10) return 0;
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writeMR(0x00);
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if (readMR() != 0x00) return 0;
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int ver = readVERSIONR_W5500();
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//Serial.print("version=");
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//Serial.println(ver);
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if (ver != 4) return 0;
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//Serial.println("chip is W5500");
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return 1;
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}
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W5100Linkstatus W5100Class::getLinkStatus()
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{
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uint8_t phystatus;
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if (!init()) return UNKNOWN;
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switch (chip) {
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case 52:
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SPI.beginTransaction(SPI_ETHERNET_SETTINGS);
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phystatus = readPSTATUS_W5200();
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SPI.endTransaction();
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if (phystatus & 0x20) return LINK_ON;
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return LINK_OFF;
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case 55:
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SPI.beginTransaction(SPI_ETHERNET_SETTINGS);
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phystatus = readPHYCFGR_W5500();
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SPI.endTransaction();
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if (phystatus & 0x01) return LINK_ON;
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return LINK_OFF;
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default:
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return UNKNOWN;
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}
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}
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uint16_t W5100Class::write(uint16_t addr, const uint8_t *buf, uint16_t len)
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{
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uint8_t cmd[8];
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if (chip == 51) {
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for (uint16_t i=0; i<len; i++) {
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setSS();
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SPI.transfer(0xF0);
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SPI.transfer(addr >> 8);
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SPI.transfer(addr & 0xFF);
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addr++;
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SPI.transfer(buf[i]);
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resetSS();
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}
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} else if (chip == 52) {
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setSS();
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cmd[0] = addr >> 8;
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cmd[1] = addr & 0xFF;
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cmd[2] = ((len >> 8) & 0x7F) | 0x80;
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cmd[3] = len & 0xFF;
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SPI.transfer(cmd, 4);
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#ifdef SPI_HAS_TRANSFER_BUF
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SPI.transfer(buf, NULL, len);
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#else
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// TODO: copy 8 bytes at a time to cmd[] and block transfer
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for (uint16_t i=0; i < len; i++) {
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SPI.transfer(buf[i]);
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}
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#endif
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resetSS();
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} else { // chip == 55
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setSS();
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if (addr < 0x100) {
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// common registers 00nn
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cmd[0] = 0;
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cmd[1] = addr & 0xFF;
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cmd[2] = 0x04;
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} else if (addr < 0x8000) {
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// socket registers 10nn, 11nn, 12nn, 13nn, etc
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cmd[0] = 0;
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cmd[1] = addr & 0xFF;
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cmd[2] = ((addr >> 3) & 0xE0) | 0x0C;
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} else if (addr < 0xC000) {
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// transmit buffers 8000-87FF, 8800-8FFF, 9000-97FF, etc
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// 10## #nnn nnnn nnnn
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cmd[0] = addr >> 8;
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cmd[1] = addr & 0xFF;
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#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
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cmd[2] = 0x14; // 16K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
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cmd[2] = ((addr >> 8) & 0x20) | 0x14; // 8K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
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cmd[2] = ((addr >> 7) & 0x60) | 0x14; // 4K buffers
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#else
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cmd[2] = ((addr >> 6) & 0xE0) | 0x14; // 2K buffers
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#endif
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} else {
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// receive buffers
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cmd[0] = addr >> 8;
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cmd[1] = addr & 0xFF;
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#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
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cmd[2] = 0x1C; // 16K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
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cmd[2] = ((addr >> 8) & 0x20) | 0x1C; // 8K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
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cmd[2] = ((addr >> 7) & 0x60) | 0x1C; // 4K buffers
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#else
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cmd[2] = ((addr >> 6) & 0xE0) | 0x1C; // 2K buffers
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#endif
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}
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if (len <= 5) {
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for (uint8_t i=0; i < len; i++) {
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cmd[i + 3] = buf[i];
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}
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SPI.transfer(cmd, len + 3);
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} else {
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SPI.transfer(cmd, 3);
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#ifdef SPI_HAS_TRANSFER_BUF
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SPI.transfer(buf, NULL, len);
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#else
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// TODO: copy 8 bytes at a time to cmd[] and block transfer
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for (uint16_t i=0; i < len; i++) {
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SPI.transfer(buf[i]);
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}
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#endif
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}
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resetSS();
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}
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return len;
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}
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uint16_t W5100Class::read(uint16_t addr, uint8_t *buf, uint16_t len)
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{
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uint8_t cmd[4];
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if (chip == 51) {
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for (uint16_t i=0; i < len; i++) {
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setSS();
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#if 1
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SPI.transfer(0x0F);
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SPI.transfer(addr >> 8);
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SPI.transfer(addr & 0xFF);
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addr++;
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buf[i] = SPI.transfer(0);
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#else
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cmd[0] = 0x0F;
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cmd[1] = addr >> 8;
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cmd[2] = addr & 0xFF;
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cmd[3] = 0;
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SPI.transfer(cmd, 4); // TODO: why doesn't this work?
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buf[i] = cmd[3];
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addr++;
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#endif
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resetSS();
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}
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} else if (chip == 52) {
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setSS();
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cmd[0] = addr >> 8;
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cmd[1] = addr & 0xFF;
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cmd[2] = (len >> 8) & 0x7F;
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cmd[3] = len & 0xFF;
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SPI.transfer(cmd, 4);
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memset(buf, 0, len);
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SPI.transfer(buf, len);
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resetSS();
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} else { // chip == 55
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setSS();
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if (addr < 0x100) {
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// common registers 00nn
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cmd[0] = 0;
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cmd[1] = addr & 0xFF;
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cmd[2] = 0x00;
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} else if (addr < 0x8000) {
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// socket registers 10nn, 11nn, 12nn, 13nn, etc
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cmd[0] = 0;
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cmd[1] = addr & 0xFF;
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cmd[2] = ((addr >> 3) & 0xE0) | 0x08;
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} else if (addr < 0xC000) {
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// transmit buffers 8000-87FF, 8800-8FFF, 9000-97FF, etc
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// 10## #nnn nnnn nnnn
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cmd[0] = addr >> 8;
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cmd[1] = addr & 0xFF;
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#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
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cmd[2] = 0x10; // 16K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
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cmd[2] = ((addr >> 8) & 0x20) | 0x10; // 8K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
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cmd[2] = ((addr >> 7) & 0x60) | 0x10; // 4K buffers
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#else
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cmd[2] = ((addr >> 6) & 0xE0) | 0x10; // 2K buffers
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#endif
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} else {
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// receive buffers
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cmd[0] = addr >> 8;
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cmd[1] = addr & 0xFF;
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#if defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 1
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cmd[2] = 0x18; // 16K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 2
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cmd[2] = ((addr >> 8) & 0x20) | 0x18; // 8K buffers
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#elif defined(ETHERNET_LARGE_BUFFERS) && MAX_SOCK_NUM <= 4
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cmd[2] = ((addr >> 7) & 0x60) | 0x18; // 4K buffers
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#else
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cmd[2] = ((addr >> 6) & 0xE0) | 0x18; // 2K buffers
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#endif
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}
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SPI.transfer(cmd, 3);
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memset(buf, 0, len);
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SPI.transfer(buf, len);
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resetSS();
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}
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return len;
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}
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void W5100Class::execCmdSn(SOCKET s, SockCMD _cmd)
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{
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// Send command to socket
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writeSnCR(s, _cmd);
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// Wait for command to complete
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while (readSnCR(s)) ;
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}
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